1. Field of the Invention
This invention relates to testing, and more particularly to the testing of very large scale integrated circuit devices.
2. Description of Related Art
Complex very large scale integrated circuits (VLSI) fabricated on a single semiconductor chip contain thousands of functional circuit elements which are inaccessible for discrete testing. Because of the complexity of the internal interconnections between circuit elements and their combinational interdependencies, testing for device integrity becomes increasingly time consuming as the number of circuit elements increases.
By way of example, if a semiconductor chip were to have fifty input connections, the number of combinations of inputs is 2.sup.50. While one could apply that number of different input patterns, record the output responses, and compare those responses with the responses that ought to result, that is a herculean task and "virtually" impossible for modern production testing.
An alternative testing protocol, is described in U.S. Pat. No. 3,614,608 (hereinafter referred to as "Giedd"). Giedd employs a random number generator to generate the test patterns. This technique considerably reduces the effort of pattern generation needed to test a device. This is true because a random pattern generator, unlike a binary counter, produces a succession of binary words wherein the split between binary zeros and ones approaches a 50% split for a substantial number of successive words. The number of words used in testing is considerably less than the total possible number of different binary counter combinations. During the random pattern test, each input to the device under test (DUT) has a 50% chance of receiving a binary zero or one input.
A second testing protocol is to employ weighted random patterns as inputs to the DUT. This technique involves applying a statistically predetermined greater number of binary ones or binary zeros to the input pins of the DUT. The object is to apply a weighted test pattern that will have a maximum effect upon the inaccessible internal circuit elements.
A further dissertation on weighted random pattern testing can be found in an article by H. D. Schnurmann et al. entitled "The Weighted Random Test-Pattern Generator", IEEE Transactions on Computers, Vol. C-24, No. 7, July 1975 at page 695 et seq. and U.S. Pat. No. 3,719,885 (herienafter referred to as "Carpenter").
Yet another technique used to improve testability is to build into the DUT additional circuit connections for the sole purpose of testing. These circuits should be kept to a minimum, consistent with testing needs, because they reduce the availability of circuits for routine functioning of the device. A device, exemplifying this built-in testability, is described in U.S. Pat. No. 3,783,254.
In order to avoid comparison of every output bit with an expected output bit, "signatures" may be used. The "signatures" are unique representations which correspond to a particular DUT output. Each signature from a DUT is compared with a "good signature". A "good signature" is the signature which is expected to result from a properly functioning DUT. The use of "signatures" in lieu of a comparison of every individual test response with a known good output response is taught by U.S. Pat. No. 3,976,864.
FIG. 1 illustrates a schematic view of the DUT 100. DUT 100 may include a number of inputs 104 and outputs 108. Between the input 104 and output 108 are sequential circuit elements e.g. 112, 116 such as flip flops and batches. These elements are coupled together in a chain 120. Other chains 124, 128 of elements may exist throughout DUT 100. In a full scan device, each chain 120, 124, 128 of elements is coupled to an input which can be clocked by a clock line 130 allowing the read-out of each element e.g. 112, 116.
Between chains 120, 124, 128 of elements 112, 116 are combinatoric logic circuits e.g. 140, 144. The logic circuits 140, 144 may include AND gates, OR gates, NOR gates and the like. In a full scan test of the DUT 100, each element 112, 116 is separately accessed and read. In a partial scan test of DUT 100 not all elements are scanned.
Prior art testing methods were suitable for applying weighted random pattern testing to full scan tests of devices. However, such full scan testing of devices is expensive. Full scan testing requires that every element e.g. 112, 116 inside a device be duplicated by a scan equivalent which enables information in the elements 112, 116 to be read out. Thus, a flop is duplicated by a scan flop, a latch is duplicated by a scan latch, such that every element can methodically be accessed by shifting information through a set of scan elements e.g. 120 including scan equivalents. As a result, full scan testing of a device is expensive.
Partial scan testing does not require that every scan element in a device under test be scanned. Instead, information input into a set of scan elements 120 can be propagated through the first set of combinatorial logic circuit elements 140 over one clock cycle and through a second set of combinatorial logic circuit elements 144 during a second clock cycle such that intermediate non-scanned sequential elements 124 can be skipped. The sequential elements 124 are pictured in a chain for convenience, but it is recognized that the sequential elements are not necessarily connected. Deterministic partial scan test patterns are more complicated and thus require significantly more tester memory to store the information. To reduce the tester memory requirements weighted random pattern testing has been used in full scan designs. However, traditional weighted random pattern testing has not been implemented on partial scan designs because weight generation in partial scan designs is orders of magnitude more complex than weight generation in full scan designs.
Thus, it is desirable to have a weighting technique for partial scans to enable weighted random testing of designs to avoid large tester memory requirements.